ET212 Grantham University Audio Amplifier Project Paper WEEK 7 Audio Amplifier Group Project Electronics I and Lab Audio Amplifier Project This is a group

ET212 Grantham University Audio Amplifier Project Paper WEEK 7 Audio Amplifier Group Project
Electronics I and Lab
Audio Amplifier Project

This is a group project which will require working with another student. The project is a design project using Multisim with the requirements given below. The project is due on the last day of the term. Refer to a design example in TOOLS and TEMPLATES.

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Project name: Audio Amplifier (Multistage).

Audio Amplifier Power Output selection: 3.2 W, 5.6 W, 7.1 W, 8.4 W, 11.5 W, and 16.3 W

Audio Amplifier Input Voltage (peak) selection: 150mVpeak, 200mVpeak, 250mVpeak

Audio Frequency: 20 Hz – 20 KHz

Deliverable: Multisim design (soft copy), test results, short report, and teamwork evaluation

Project Definition:

Design, simulate, and test an Audio Amplifier which delivers one of the above power outputs to an 8Ω speaker load. The output power of your design and the input signal of your design must be selected from the above list. The audio frequency range is between 20 Hz to 20 KHz, so the operating frequency of your design will be within this range. The measuring equipment should display the output power and the input signal of your design. You are required to use either or both NPN and PNP transistors, but not an op-amp. It is recommended that you use multistage amplification of any class amplifiers of your choice. You should try to minimize your usage of components and be cost effective.

Project Structure:

In general, you will have one other classmate in your team. Each of you will design and simulate an audio amplifier with different specifications, each making your choice from the above parameters. Thus, it is highly suggested that you communicate with your partner as early as possible to plan and coordinate your activities, select the input voltage and output power for your design, and establish a schedule. For the testing phase, you will develop a test plan and characterize and validate your teammate’s amplifier.

During the project period, you are encouraged to communicate, exchange ideas, and help each other complete your project. A team area will be set up for you in Blackboard, and you are required to use this area as part of your grade will be based on effectively using this tool.

Project Deliverable: Report and the multisim design for your project

Each student will submit an individual report. The report should, as a minimum, include the following:

Title Page (Name, Partners name, like the table they have in the document)
Description of your project (including the specifications you selected)
Design methodology (show calculations and provide rationale for design choices; remember that your choices must take into consideration commonly available parts)
Final schematic in Multisim
Components/Parts list with cost and total project cost
Simulation results for your design
Testing process and results for characterization and validation of your teammate’s design – screenshots along will not suffice. Description of process is required along with discussion of results.
Project Challenges: Note any difficulties you faced during the completion of your design and how you overcame them
Team Interaction Reflection: Describe how you used Blackboard to facilitate interaction, how you worked with one another in the design phase, challenges you encountered, methods you employed to overcome any challenges.
Teammate Assessment: Use the Project Participation Rubric below and give your teammate a ranking of Needs Improvement, Competent, or Excellent for the first two items in the rubric: Interacts professionally and Plans and organizes team effort. Be sure to justify your ranking.
Class A Power Amplifier Design
1. This is the amplifier configuration I want you all to use for your project. It has 2 voltage amplifier
stages using the 2N3904 and one power amplifier stage which amplifies current. The power
amplifier stage has a special, 2 transistor connection called a Darlington Pair. The Vbe for this device
is approximately 1.4 volts. Internally the betas multiply giving a very high current gain. The voltage
gain of the power amplifier is close to 1. It has a very high input impedance because of the high Beta
value and biasing resistors in the voltage divider. This is a CLASS A power amplifier. You will learn
more about these in the next semiconductor class. The total voltage gain of the multistage
amplifiers multiply. Atot = Astage1 x Astage2 x Astage3(the letter ‘A’ represents the gain multiplication
factor. An amplifier that has a gain of 10 (A = 10); if you put in 1mV, you get out 10mV at the
2. I am going to give you a step by step procedure to design the power amplifier stage. Example
a. Output power = 4 W
b. Operating frequency 20 Hz to 20kHz
3. Determine the current and voltage at the 8 ohm load.
7. The power supply should be greater than 16 Vdc. We can set the initial value of Vcc to 20 Volts. We
can increase it if it is necessary to prevent clipping of the output signal.
8. The Q point of the 2N6038 Darlington can be estimated from the peak to peak values. We want to
bias the transistor as close to the center of the load line. We can let Vce = to ½ of Vout = 8
volts. Ic = ½ Iout = 1 A. When choosing the transistor you must make sure the device can handle the
voltage and current. The no signal power of the transistor = 8 volts x 1 A = 8 W. The specification for
the 2N6038 is 60 volts Vce and 4 amps Ic so it is capable to handling the power requirements.
Note: When using high power transistors, you may have to do a design of a proper heatsink to
protect the device. We will not look at that in this tutorial.
9. We can calculate the value of the emitter resistor. If the voltage across the transistor is 8 volts,
assume the remaining voltage is across the resistor = 8v. The current through the resistor is 1 A. The
value of RE = 8V / 1 A = 8 Ω.
10. Calculate the voltage divider resistor values R2 and R3.
a. Find the beta of the transistor from the datasheet. The typical value of Beta (HFE) =
2000. You can also estimate the value by taking the Geometric Mean of the maximum
and minimum values
For now we’ll use the value of 2000.
b. We will let the voltage divider resistors equal one another. The parallel combination will
be Rth. We’ll apply the formula to calculate Rth.
c. The value of each resistor in the voltage divider = 2 x
= 3.2 kΩ. Note, the bottom
resistor R3 may have to be increased to remove clipping of the output signal and give
you the correct power output.
11. The lowest frequency is 20 Hz. To calculate the value of C1 use the formula below.
12. When you design a circuit, you obtain some initial values based on theory, build it, test it and make
adjustments to get what you need.
13. The input impedance must be calculated because the power amplifier is the load for the middle
voltage amplifier stage and will be needed in the design of the middle amplifier stage.
Note: The symbol || means in parallel with, example
R2 || R3 =
Results of initial values
14. As you can see, we are getting clipping at the output so adjustments need to be made for the power
amplifier stage. We’ll try increasing the power supply voltage and the R3 resistor and we get the result
below, an output that is not distorted giving us close to 4 W of power out.
1. From the power amplifier stage, I indicated that the input impedance was 1.33k ohm. That is
the load for the middle amplifier stage. The circuit above uses negative feedback to reduce and
control the gain (using R13 and R14).
2. Determine the voltage gain for stage 1 (Q3), and stage 2 (Q2). The overall gain is
Av stage1 x Av stage2. The Vout of stage 3 (Q1) was 16 Vp-p. If the specification was a Vin of
25mVpeak was the input to the amplifier, the overall voltage gain is Vout/Vin = 16Vp-p / 50p-p =
320. Assume Beta = 100.
3. You can make a choice for the voltage gain for each stage. Let’s let stage 2 have a gain of 32 and
stage 1 have a gain of 10.
4. Design the DC biasing for the middle stage. Let Vce = 1/3 to ½ of Vcc. That should be a voltage
from 11 to 16V. We can try letting Vce = 1/3 of Vcc (11 volts). Let Rc = Re = ½ of Zin of the
power amplifier which is 1.33k / 2 = 665Ω, use 680 Ω for the closest standard value.
5. We can calculate the current IC = VRC / RC = 11V / 680Ω = 16.2mA.
6. For VR7 add .7 volts to 11 volts to make it 11.7 volts. VR6 = VCC – VR7 = 32V – 11.7v = 20.3V.
7. To find out how much larger R6 is than R7 divide the values to get a multiplication factor;
20.3/11.7 = 1.74
8. For R6 and R7 follow this rule of thumb:
For IE stability RE should be at least 10 times greater than Rth/Beta from the formula
IE = (VB – .7)/ (RE + (Rth/Beta))
(Rth = R6 in parallel with R7 calculation)
RE = 680Ω, Beta = 100,
RE = 10 (Rth/Beta) solving for Rth
Rth = (RExBeta)/10 = (680 x 100)/10 = 6.8k. Let R7 = 6.8k.
Let R6 = Multiplication factor x R7 = 1.74 x 6.8k = 11.8k, use 12k for a close standard value.
9. We need to make sure the 2N3904 can handle the voltage and current. The maximum VCE =
32V, the maximum current is VCC / (RE + RC) = 32V / (680Ω + 680Ω) = 23.5mA. The 2N3904 can
handle a maximum voltage of 40 volts and 200mA (this is the absolute maximum rating from the
datasheet). You never operate a component at the absolute maximum rating to prevent
damage. The 2N3904 can handle the current and voltage that is calculated.
10. Build the DC biasing network and test and make any value adjustments to the resistors to
get Vce and IE close.
11. For the AC portion of the design the components that determine the voltage gain of the middle
amplifier stage are RC, Zin of the power amplifier stage, r’e, and R13.
Av = rC / (rE + r’e) = (R8||Zin)/ (r’e + R13). Make adjustments in R13 to get the desired gain after
calculation of Av.
12. For the middle stage Q2, we chose a gain of 32 so rC = 680 || 1.33k = 450 ohms,
(r’e + R13) = 450 ohms / 32 = 14.1 ohms, r’e = 25mV/16.2mA = 1.6 ohms,
R13 = 14.1 ohms – 1.6 ohms = 12.5 ohms, use 12 ohms for the closest standard value. You may
have to adjust this value to get the exact gain you need.
13. To get the capacitor values refer to week 6 homework on capacitor values. In this example for
C2, Xc should be 1/10 maximum of Zin of the power amplifier (1.33k) at the lowest specified
frequency 20Hz.
14. C = 1/(2πFXc) = 1/(2π x 20Hz x 133 ohms) = 59.86uF, you can make it larger, I chose 100uF for
the coupling capacitor C2 for the middle stage.
The bypass capacitor C3 should have an Xc no larger than 1/10 of R13 at 20Hz. Using the same
formula C =5670uF. NOTE: IF R13 WAS NOT IN THE CIRCUIT, XC = 1/10 OF RE (R5).
15. Find Zin of the middle stage.
Zin = R6||R7||[Beta x (r’e + R13)] = 12k || 6.8k|| [100x(1.6 Ω+ 12Ω)] = 1.03kΩ
Capacitor C4 = 1/[2π(103Ω x 20Hz)] = 77.29uF, use 100uF.
16. Use the generator to test the middle and last stage. Apply 500mV p-p to C4. You should get
close to 16Vp-p out without clipping.
If clipping occurs when the AC signal is applied, you may have to adjust R6 & R7 values first and
possibly RE & RC to adjust the Q point.
17. Once the 2 stages are fine-tuned, we can design the input stage that has Q3. It should have a
gain of 10. Follow the procedures above to design the stage and make appropriate adjustments.
The input to this stage will be 50 mVp-p.
18. Test the circuit at 20Hz to make sure you get the power out at the lowest frequency.

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